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INTEGRATED CIRCUITS
DATA SHEET
TDA8961 ATSC Digital Terrestrial TV demodulator/decoder
Objective specification File under Integrated Circuits, IC02 2000 May 19
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
FEATURES General features * One-chip ATSC-compliant demodulator and concatenated trellis (Viterbi)/Reed Solomon decoder with de-interleaver and de-randomizer * 0.35 m process * 3.3 V device * QFP80 package * Boundary Scan Test (BST) * 12 MHz external clock * 36 MHz output for external D/A converter * Parallel or serial MPEG-2 transport stream output. 8-Vestigial Side Band (VSB) demodulator * Accepts 10-bit IF data sampled at 36 MHz * 6 MHz wide IF signal, centered at 4 MHz * On-chip digital circuitry for tuner AGC * Square-root raised-cosine filter with 11.5% roll-off factor * Fully internal carrier recovery loop * No need for external voltage controlled crystal oscillator due to internal sample rate converter * Fully internal symbol timing recovery with programmable loop filters * Technology to handle dynamic multipath conditions. Adaptive equalizer * Including feed forward and feedback sections with Decision Feedback Equalizer (DFE) structure * Range of -2.3 to +22.5 s by default (in conjunction with external software, -2.3 to +80 s) * Adaptation based on ATSC field sync (trained) and/or 8-VSB data (blind). NTSC co-channel interference filter Patented NTSC co-channel interference technology with low noise penalty. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA8961 QFP80 DESCRIPTION plastic quad flat package; 80 leads (lead length 1.95 mm); body14 x 20 x 2.8 mm On-chip forward error correction * Trellis (Viterbi) decoder
TDA8961
* Rate 23 (Rate 12 Ungerboeck code based) * (207, 187, T = 10) Reed Solomon code * Internal convolutional de-interleaving (I = 52; using internal memory) * External indication of uncorrectable error; transport_error_indicator bit in MPEG packet header is also set * De-randomizer based on ATSC standard * Segment error rate readable through I2C. I2C interface I2C-bus interface to initialize and monitor the demodulator and Forward Error Correction (FEC) decoder. An operation without I2C-bus is possible (default). System interfaces * 8-bit wide or serial MPEG-2 transport stream interface * ITU656 bypass mode * MPEG-2 serial transport stream input to reduce external components when the IC is combined in a system with a Quadrature Amplitude Modulation (QAM), Quadrature Phase Shift Keying (QPSK) or Orthogonal Frequency Division Multiplexing (OFDM) channel decoder. APPLICATIONS * Digital ATSC compliant TV receiver * Personal computers with digital television capabilities * Set top-boxes.
VERSION SOT318-2
2000 May 19
2
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
GENERAL DESCRIPTION The TDA8961 is an Advanced Television Systems Committee (ATSC)-compliant demodulator and FEC decoder for reception of 8-VSB modulated signals for terrestrial and cable applications: * Terrestrial: reception of 8-VSB modulated signals via standard 6 MHz VHF/UHF terrestrial TV channels (TV channels 2 to 69 in the United States). * Cable: reception of 8-VSB modulated signals via standard 6 MHz VHF/UHF cable TV channels. An application using the TDA8961 and the TDA8980 NTSC/ATSC TV input processor for TV and Multi-Media is shown in Fig.1. A tuner converts the incoming RF signal to a fixed IF centered at 44 MHz. The output signal from the tuner is filtered and fed to the TDA8980 which performs the following functions: * Decodes the analog NTSC signals: The audio signals are digitized, using on-chip audio stereo A/D converters, into an I2S-bus stream; the video information is digitized, using on-chip video A/D converters, into an ITU656 stream.
TDA8961
* Down converts the incoming 6 MHz wide 8-VSB IF signal to a low-IF signal centered at 4 MHz: The low-IF signal is then digitized, using an on-chip 10-bit A/D converter, and fed to the TDA8961 for further processing. In this application, AGC is also managed by the TDA8980 so that no other external components, such as an operational amplifier loop integrator, are required. Although the TDA8980 has an internal 2-D comb filter, external filters such as a 3-D comb filter and other picture improvement devices can easily be connected. Sound can be decoded using an external device such as the TDA9851 I2C-bus controlled economic BTSC stereo decoder. This IC has an internal switch allowing it to process either analog NTSC IF or digital 8-VSB IF signals. A 12 MHz clock signal is generated using a 12 MHz crystal connected to the TDA8980. The TDA8961 also uses this clock signal which is fed from the TDA8980 to pin XTALI of the TDA8961.
handbook, full pagewidth
TUNER
NTSC SAW FILTER FLAT SAW FILTER
TDA8980
TVIFIN VCLK D9 to D0 VSBIFIN TUNERAGC I2C X12MOUT X12MIN REF12M VIFAGC ADCLK ADIN9 to ADIN0 XTALI AGCOUT
TDA8961
PDOVAL PDOERR PDO7 to PDO0 PDOSYNC PDOCLK MPEG-2 transport stream
I2C
12 MHz I2C PDI0 PDISYNC PDIVAL PDICLK PDIERR
MGU085
serial MPEG-2 transport stream input I2C master
Fig.1 Front-end design for a hybrid TV system using the TDA8980 and TDA8961.
2000 May 19
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
The incoming data has a sample rate of 36 MHz. This is internally converted to a sample rate of 21.52 MHz which is twice the 8-VSB symbol rate. This patented Philips Semiconductors' technology eliminates the need for external symbol timing recovery loop components. When the TDA8980 is decoding analog NTSC, the TDA8961 can be set to a ITU656 bypass mode which allows the 8-bit ITU656 data output from the TDA8980 to appear at the TDA8961 Moving Pictures Expert Group (MPEG-2) transport stream output, from where it can be fed to the main graphics display device in the system. The recovery of the carrier is performed entirely within the TDA8961. This function consists of a digital frequency and Frequency Phase-Locked Loop (FPLL). Data shaping is performed by a square-root raised-cosine (half Nyquist) filter having a roll-off factor of 11.5%. After the TDA8961 has performed carrier recovery, Nyquist filtering and symbol timing recovery, it then performs adaptive equalization. The adaptive equalizer uses a DFE structure with equalization based on the ATSC field sync (trained equalization) and/or the 8-VSB data itself (blind equalization). The equalizer is followed by a patented NTSC co-channel interference filter which removes any unwanted NTSC signal interference from the 8-VSB terrestrial DTV signal. After trellis decoding, the stream is de-interleaved to a depth of 52 by a convolutional de-interleaver whose memory is provided on-chip. The Reed Solomon decoder is ATSC-compliant, with a length of 207, and able to
TDA8961
correct up to 10 bytes. The decoded stream is then de-randomized using a pseudo-random binary sequence (PRBS) and the data passed to a FIFO which prevents the appearance of irregular gaps in the output data. The output of the TDA8961 is a clock signal and an ATSC-compliant MPEG-2 packetized data stream. Signal flag outputs are provided to indicate the occurrence of sync bytes, valid data bytes and uncorrected Reed Solomon blocks. The packetized data stream is available in either an 8-bit parallel, or a 1-bit serial format for connection to an MPEG-2 transport stream demultiplexer. An application using the TDA8961 and a stand-alone TDA9829 Downconverter for DVB (Digital Video Broadcast) with an A/D converter is shown in Fig.2. A tuner converts the incoming RF signal to a fixed IF centered at 44 MHz. The output signal from the tuner is filtered using two Surface Acoustical Wave (SAW) filters and then down converted to an IF of 4 MHz by the TDA9829. The signal is then digitized by an A/D converter at a sample rate of 36 MHz using the clock signal output from the TDA8961. The full input range of the A/D converter is utilized by placing it within what is effectively a fine-AGC loop integrator circuit which has a variable gain stage at the output of the IF downmixer section. However, it is also possible to apply the AGC control output of the TDA8961 to the tuner via the integrator. The peak level of the input signals to the TDA8961 is determined by the AGC output detector which is located just after the A/D.
handbook, full pagewidth
integrator AGC Vref 44 MHz VAGC ViIF VoDVB A D AGCOUT ADIN9 to ADIN0 ADCLK CLK36 XTALI 12 MHz
MGU086
RF
SAW FILTER TUNER RF
SAW FILTER
TDA9829
IF DOWNMIXER VCO 96 MHz OSCILLATOR
PDO7 to PDO0
TDA8961
MPEG-2 transport stream
/8
Fig.2 Front-end design for the TDA8961 using a stand-alone IF down converter (TDA9829) and A/D converter.
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
QUICK REFERENCE DATA SYMBOL VDD IDD fclk fsym fs fc(IF2) IL ro tacq Tamb Ptot Note 1. Corresponds to 12 training sequences. PARAMETER supply voltage supply current clock frequency symbol frequency sample frequency second IF centre frequency implementation loss half Nyquist filter roll-off factor acquisition time ambient temperature total power dissipation note 1 VDD = 3.3 V CONDITIONS - - - - - - - - -20 - MIN. 2.7 TYP. 3.3 390 12 10.76 36 4 - 11.5 - - 1.3 - - - - - - - 290 +70 -
TDA8961
MAX. 3.6 V mA
UNIT
MHz Msymbols/s MHz MHz dB % ms C W
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
BLOCK DIAGRAM
TDA8961
handbook, full pagewidth
ADIN9 TO ADIN0 10, 9, 8, 7, 6, 5, 4, 3, 2, 1 TMS TDO TDI TRST TCK 20 23 19 22 21 DIGITAL FRONT-END: BOUNDARY SCAN TEST CONTROLLER
ADCLK 80
LOCKINDIC EQLOCKINDIC RST_AN
78 79 77 CONTROL
* SAMPLE RATE CONVERTER * FINE AGC 66 * CARRIER RECOVERY HALF NYQUIST FILTERING * * SYNC RECOVERY AND PILOT REMOVAL * SYMBOL TIMING RECOVERY * ADAPTIVE EQUALIZATION
AGCOUT
NTSC CO-CHANNEL INTERFACE FILTER
A0 A1 SCL SDA
13 TRELLIS DECODER 14 15 16 I2C-BUS INTERFACE DE-INTERLEAVER
XTALI XTALO CLK36
69 70 75 CLOCK GENERATION
REED SOLOMON DECODER
DE-RANDOMIZER
PDISYNC PDICLK PDIERR PDIVAL PDI0
26 30 32 28 27
OUTPUT FORMATTER
TDA8961
34 35 67 39 40
43, 44, 45, 47, 48, 49, 51, 52 37
41
MGU087
FSYNC FSHNDSHK SSYNC
PDOCLK PDOSYNC PDO7 TO PDO0 PDOVAL PDOERR
Fig.3 Block diagram.
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
PINNING SYMBOL ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 ADIN5 ADIN6 ADIN7 ADIN8 ADIN9 VDDD1 VSSD1 A0 A1 SCL SDA VDDD2 VSSD2 TDI TMS TCK TRST TDO VDDD3 VSSD3 PDISYNC PDI0 PDIVAL VDDD4 PDICLK VSSD4 PDIERR VDDD5 FSYNC SSYNC VSSD5 PDOERR VDDQ1 PDOSYNC PDOVAL 2000 May 19 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I I I I I I I I I I - - I I I I/O - - I I I I O - - I I I - I - I - I I - O - O O data input bit 0 (LSB) data input bit 1 data input bit 2 data input bit 3 data input bit 4 data input bit 5 data input bit 6 data input bit 7 data input bit 8 data input bit 9 (MSB) digital core supply voltage 1 (3.3 V) digital core ground 1 I2C-bus slave address bit 0 I2C-bus slave address bit 1 I2C-bus clock I2C-bus serial data I/O supply (3.3 V) digital core ground 2 TAP controller data input; note 1 TAP controller test mode select; note 1 TAP controller test clock; note 1 DESCRIPTION
TDA8961
TAP controller asynchronous reset (active LOW); notes 1 and 2 TAP controller test data (3-state); note 1 digital core supply voltage 3 (3.3 V) digital core ground 3 transport stream interface packet sync indicator transport stream interface packet data bit 0 transport stream interface packet data valid signal digital core supply voltage 4 (3.3 V) transport stream interface packet data clock signal digital core ground 4 transport stream interface packet error signal digital core supply voltage 5 (3.3 V) field sync strobe (for debug modes) segment sync strobe (for debug modes) digital core ground 5 transport stream interface packet error signal (3-state) I/O supply voltage 1 (3.3 V) transport stream interface packet sync indicator signal (3-state) transport stream interface packet data valid indicator signal (3-state) 7
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
SYMBOL PDOCLK VSSQ1 PDO7 PDO6 PDO5 VDDQ2 PDO4 PDO3 PDO2 VSSQ2 PDO1 PDO0 VDDQ3 n.c. n.c. VSSQ3 n.c. n.c. n.c. VDDQ4 n.c. n.c. n.c. VSSQ4 n.c. AGCOUT FSHNDSHK VDDA1 XTALI XTALO VSSA1 VDDA2 n.c. VDDQ5 CLK36 VSSQ5 RST_AN LOCKINDIC EQLOCKINDIC ADCLK PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 - O - I O O I O O - I O - - - - - I/O O - O O O - O O O - O O - I/O ground 1 transport stream interface packet data bit 7 (3-state) transport stream interface packet data bit 6 (3-state) transport stream interface packet data bit 5 (3-state) I/O supply voltage 2 (3.3 V) transport stream interface packet data bit 4 (3-state) transport stream interface packet data bit 3 (3-state) transport stream interface packet data bit 2 (3-state) I/O ground 2 transport stream interface packet data bit 1(3-state) transport stream interface packet data bit 0 (3-state) I/O supply 3 (3.3 V) not connected not connected I/O ground 3 not connected not connected not connected I/O supply 4 (3.3 V) not connected not connected not connected I/O ground 4 not connected AGC control (3-state) DESCRIPTION
TDA8961
transport stream interface packet data clock signal (3-state)
field sync strobe or symbol capture memory handshake signal analog supply voltage (3.3 V) external crystal external crystal analog ground 1 analog supply 2 (3.3 V) not connected I/O supply 5 (3.3 V) 36 MHz clock signal I/O ground 5 asynchronous reset (active LOW) front-end lock indicator equalizer lock indicator incoming data sampling clock signal (36 MHz)
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
Notes
TDA8961
1. Input pins TCK, TDI, TMS and TRST have an internal pull-up transistor and must be connected to ground when not used; pin TDO is a 3-state output in accordance with IEEE 1149.1. 2. Pin TRST is active LOW. It can be used to immediately force the Test Access Port (TAP) controller to the test logic reset state (normal operation) in accordance with IEEE 1149.1.
2000 May 19
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
TDA8961
79 EQLOCKINDIC
67 FSHNDSHK
78 LOCKINDIC
66 AGCOUT
77 RST_AN
74 VDDQ5
76 VSSQ5
72 VDDA2
68 VDDA1
80 ADCLK
70 XTALO
71 VSSA1
75 CLK36
69 XTALI
73 n.c.
handbook, full pagewidth
65 n.c. 64 VSSQ4 63 n.c. 62 n.c. 61 n.c. 60 VDDQ4 59 n.c. 58 n.c. 57 n.c. 56 VSSQ3 55 n.c. 54 n.c. 53 VDDQ3 52 PDO0 51 PDO1 50 VSSQ2 49 PDO2 48 PDO3 47 PDO4 46 VDDQ2 45 PDO5 44 PDO6 43 PDO7 42 VSSQ1 41 PDOCLK PDOVAL 40
MGU088
ADIN0 ADIN1 ADIN2 ADIN3 ADIN4 ADIN5 ADIN6 ADIN7 ADIN8
1 2 3 4 5 6 7 8 9
ADIN9 10 VDDD1 11 VSSD1 12 A0 13 A1 14 SCL 15 SDA 16 VDDD2 17 VSSD2 18 TDI 19 TMS 20 TCK 21 TRST 22 TDO 23 VDDD3 24 VSSD3 25 PDISYNC 26 PDI0 27 PDIVAL 28 VDDD4 29 PDICLK 30 VSSD4 31 PDIERR 32 VDDD5 33 FSYNC 34 SSYNC 35 VSSD5 36 PDOERR 37 VDDQ1 38 PDOSYNC 39
TDA8961
Fig.4 Pin configuration.
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
FUNCTIONAL DESCRIPTION The internal architecture of the TDA8961 basically comprises two parts: * The front-end: containing the AGC, carrier recovery, half Nyquist filter, symbol timing recovery, sync recovery and adaptive equalization sections. * The back-end: containing the NTSC co-channel rejection filter, trellis decoder, de-interleaver, the Reed Solomon decoder and de-randomizer sections. Sample rate converter INTRODUCTION The sample rate converter section changes the incoming data frequency of 36 MHz to an internal sampling frequency of twice the symbol rate. The 10-bit wide data from either the TDA8980 or a stand-alone A/D converter (TDA8763A is recommended) arrives at the sample rate converter input of the TDA8961 via inputs ADIN9 to ADIN0. The format of the incoming samples can be programmed by the status of I2C-bus bit AD_FMT (see Table 9). The format can be either two's complement or binary. The default setting is binary to comply with the TDA8980. PINNING The functions of the input interface pins are given in Table 1. If a stand-alone A/D converter is used, pin CLK36 is connected externally to pin ADCLK. Table 1 Input interface NAME ADIN9 to ADIN0 ADCLK CLK36 Table 2 AGC COMPARATOR OUTPUT 1 0 1 0 Z I2C-bus bit AGC_DIR 0 0 1 1 0 36 MHz clock signal input FUNCTION 10-bit data input (from external A/D converter) Fine AGC
TDA8961
The fine AGC section controls the gain of analog signals over a range of 20 dB. The level of the signal at pins ADIN9 to ADIN0 is monitored and an average level from several samples is acquired. The default number of samples is 64, but this value can be set to 256 by setting I2C-bus bit AGC_SAMPLES (see Table 10). A comparator compares the level of the filtered signal with a threshold level represented by a signed four-bit value set by I2C-bus bits AGC_TR_LOW. The comparator output determines the level at pin AGCOUT which is used to either charge or discharge an off-chip ideal integrator, which in turn, controls the gain of the tuner front-end module. To make the level at pin AGCOUT compatible with the AGC circuits in other devices, the comparator output can be inverted by setting I2C-bus bit AGC_DIR (see Table 10). The default value of bit AGC_DIR is 0 making the output at pin AGCOUT compatible with the AGC circuit in the TDA8980. The levels at pin AGCOUT with respect to the value of bit AGC_DIR are shown in Table 2. The AGC section can be reset by setting I2C-bus bit AGC_RESET (see Table 8).
clock signal output for sampling incoming data (to external A/D converter)
FILTER OUTPUT LEVEL Above threshold Below threshold Above threshold Below threshold Equal to threshold
Pin AGCOUT 1 0 0 1 Z
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
Carrier recovery The carrier recovery circuit recovers the frequency and phase of the pilot carrier signal. If, as in some cases, the pilot signal is present at the higher edge of the VSB spectrum, the I2C-bus bit CR_INV can be set to ensure that when the frequency is shifted, the pilot signal is DC. Half Nyquist filtering The half Nyquist filtering section is a square-root raised-cosine filter with 11.5% roll-off. Sync recovery The sync recovery section performs several functions including the recovery of segment sync and field sync. When this section detects the data segment sync signal, pin LOCKINDIC goes HIGH. The status of pin LOCKINDIC can also be read via the I2C-bus bit LOCK_INDICATOR (see Table 16). Timing recovery The timing recovery section takes signals from the half Nyquist filter and forms part of a closed loop in order to acquire and maintain a constant sampling rate and clock frequency for the complete system. Adaptive equalizer The adaptive equalizer comprises a forward filter and a feedback filter section. At every symbol period, it receives demodulated symbols from the sync recovery section. The equalizer filters these symbols in an attempt to eliminate the effects of multipath conditions on the symbol stream during transmission. The coefficients of the filters are updated every symbol period using the training sequence and/or using blind equalization if required. The equalizer is designed to correct a maximum pre-echo of 2.32 s and a maximum post-echo of 22.5 s. The equalizer has an optimized typical acquisition time of 12 training sequences, which corresponds to about 290 ms. It is defined that acquisition occurs when the output signal-to-noise ratio reaches the Threshold Of Visibility (TOV). For 8-VSB, the ATSC defines a TOV of 14.9 dB. A Mean Square Error (MSE) signal is generated based on the training signal and on the output of the equalizer. The error signal represents a 16-bit value which is read via the I2C-bus bit MSE (see Table 18) and used to monitor the channel adaptation process. It is possible to use software control to extend the range of the feedback filter to a maximum of 80 s. 2000 May 19 12 CONTROL
TDA8961
An integrated sophisticated finite state machine controls the sequence of operations that must be performed to correctly decode a valid VSB data signal into an MPEG-2 packetized transport stream. After a reset has been applied, the finite state machine is in state 0. When a valid VSB data signal is detected, the finite state machine ensures that the following three states occur.
State 1: channel acquisition
In this state there is either no channel signal present or a channel signal is in the process of being acquired. Before the channel signal can be acquired, the AGC, timing recovery and carrier recovery loops must first lock onto it. If segment sync lock is lost, either pin LOCKINDIC goes LOW, or a hardware reset is applied to the TDA8961 and the finite state machine returns to state 0.
State 2: equalizer training
The finite state machine remains in state 1 until the MSE of the equalized training sequence falls between two specific threshold values. It should be noted that in state 1, the back-end section of the TDA8961 is continuously reset to make sure that after its demodulator has locked onto a signal, the trellis decoder and the following sections begin processing at the start of the next complete data field. The value of I2C-bus bit MSE can be used for applications such as antenna pointing.
State 3: normal operation
Normally the finite state machine remains in state 2 unless a synchronization error occurs. If the MSE of the equalized training sequence exceeds 100 ms, the equalizer is reset for one symbol period and the adaptation process restarts. If the demodulator synchronization and equalization are both locked, pin EQLOCKINDIC goes HIGH and I2C-bus bit LOCK_INDICATOR is set to 11 (see Table 16). The filtered output signal is then routed to the NTSC co-channel interference filter. NTSC co-channel interference filter The NTSC co-channel interference filter uses patented Philips' technology making its performance considerably better than the ATSC specified comb filter. The filter can be bypassed by setting I2C-bus bit FLT_BYPASS (see Table 13).
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
Transport stream interface INTRODUCTION The transport stream interface performs the following functions: * Buffers the data from the Reed Solomon decoder and de-randomizer section * Inserts the MPEG sync byte at the start of every packet * Indicates error conditions using a transport_error_indicator bit in the packet header and the error signal output PDOERR. * Outputs either a serial or a parallel output format. PINNING The functions of the transport stream interface outputs are summarized in Table 3. It should be noted that different source decoder devices may have different uses for the PDOERR output; its polarity is programmable using I2C-bus bit FPBP (see Table 14). PARALLEL OUTPUT FORMAT Figure 5 shows the timing diagram for the parallel output format. The PDOSYNC signal indicates the occurrence of the sync byte in the packet and is only HIGH for one clock period. The polarity of the PDOVAL and PDOERR signals is programmable via I2C-bus bits FDVP and FPBP respectively; Fig.5 shows their default polarities. The PDOVAL signal is active for the duration of the 188 bytes of the transport stream packet. When the 188 bytes have been transferred, the PDOVAL signal goes LOW for at least ten PDOCLK cycles during which, Table 3 Transport stream interface outputs All pins are 3-state outputs. SYMBOL PDOCLK PDOVAL PDO7 to PDO0 PDOSYNC PDOERR Note 1. In serial output format, only pin PDO0 (LSB) is used to output the data. indicates a valid data signal packet data bits 7 to 0 (8-bit wide output bus)(1) FUNCTION clock signal for MPEG-2 packet data bytes (parallel and serial)
TDA8961
when used with DVB devices, the parity bytes are transferred; when used with non-DVB devices, zeroed parity bytes and field sync data are transferred. The period when the PDOVAL signal is LOW can vary, but will be a minimum of ten PDOCLK cycles. Due to the averaging operation of the FIFO, the number of parity bytes transferred can vary slightly. The PDOCLK signal runs continuously and is not affected by a reset. In parallel output format, it has a frequency of 3 MHz. When the TDA8961 is trying to acquire a channel, the PDOERR signal goes HIGH (I2C-bus bit FPBP = 1). If this occurs, the PDOVAL signal stays LOW. SERIAL OUTPUT FORMAT Figure 6 shows the timing diagram for the serial output format. The LSB of the 8-bit PDO data bus is used to output the MPEG-2 transport stream packets. The PDOSYNC signal indicates the occurrence of the sync byte in the packet and is only HIGH during 8 PDOCLK cycles. The polarity of the PDOVAL and PDOERR signals is programmable via I2C-bus bits FDVP and FPBP respectively; Fig.6 shows their default polarities. The PDOVAL signal is active for the duration of the 188 bytes of the transport stream packet. When the 188 bytes have been transferred, the PDOVAL signal goes LOW for a period corresponding to the duration of the parity and field sync information. Figure 6 shows the PDOERR signal is HIGH for the whole packet length indicating that the packet contains errors. The PDOCLK signal has a frequency of 27 MHz.
indicates the start of a packet; goes HIGH at the start of a packet and stays HIGH during the first byte, otherwise known as the sync byte indicates packet error; goes HIGH (I2C-bus bit FPBP = 1) for every packet (188 bytes) in which the Reed Solomon decoder found more errors than it could correct
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
TDA8961
handbook, PDOCLK full pagewidth
PDO7 to PDO0 PDOSYNC
20
(1)
1
2
186
187
(2)
(2)
(2)
(2)
(1)
1
PDOVAL
(3)
PDOERR
(3)
MGU090
(1) Sync byte. (2) Parity byte; contents set to 00H. (3) The polarity of these signals is programmable.
Fig.5 Parallel output format.
handbook, full pagewidth PDOCLK
PDO0
MSB
6
5
LSB
7
6
0
7
0
7
6
0
7
0
PDOSYNC
(1)
PDOVAL
(2)
PDOERR
(2)
MGU091
sync byte (47H)
byte 1
byte 187
(1) Sync byte. (2) The polarity of these signals is programmable.
Fig.6 Serial output format.
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
SYNC BYTE AND TRANSPORT STREAM ERROR INDICATOR Figure 7 shows the structure of the so-called transport stream packet header of which only the first two bytes are significant to the TDA8961. The first byte in each header is the sync byte which must have the same value for all packets in accordance with the MPEG-2 standard specification. The TDA8961 sets the sync byte for each outgoing transport stream packet to 47H. The MSB of the second byte in the header is the transport_error_indicator bit. It is asserted when the Reed Solomon decoder is unable to correct all errors in the transport stream packet and indicates that the packet contains invalid data. To perform bit error rate (BER) measurements, the external channel decoder generates a pseudo-random bit sequence (PRBS) in the last 187 bytes of each transport stream packet.The same PRBS signal is generated within the BER tester which compares it with the PRBS in each transport packet and records any mismatch as an error. It should be noted that during BER measurements, the TDA8961 must not be allowed to set the transport_error_indicator bit. This option is possible using I2C-bus bit FTEI (see Table 14). If bit FTEI is not set, the transport error interface bit is not allowed to indicate an error. If bit FTEI is set, the Reed Solomon decoder is allowed to set the transport_error_indicator bit according to the result of the error correction process. This is the default setting. SERIAL TRANSPORT STREAM INPUT
TDA8961
The TDA8961 can be used with another channel decoder without requiring the transport stream outputs from either decoder to be selected by an external switch. This configuration requires the serial transport stream output from the other channel decoder to be connected to the serial transport stream input of the TDA8961. When the system requires the transport stream from the other channel decoder, the TDA8961 internally connects PDIERR to PDOERR, PDIVAL to PDOVAL, PDICLK to PDOCLK, PDISYNC to PDOSYNC and PDI0 to PDO0 allowing the transport stream from the other channel decoder to pass through the TDA8961. This pass-through mode is enabled by setting the value of I2C-bus TSMODE bits to 11 (see Table 14). ITU656 BYPASS MODE Figure 1 shows the tuner output connected to the TDA8980 which processes the IF and then outputs an 8-bit wide MPEG-2 transport stream to the TDA8961 where it is further processed before it is output to the video processor. This arrangement allows one system to receive both analog and digital broadcasts. When analog signals are received, the TDA8980 supplies an ITU656 format video stream to the TDA8961 input interface comprising pins ADIN9 to ADIN0 and ADCLK. The ITU656 format uses 8-bit data and a 27 MHz clock signal.
handbook, full pagewidth
188 bytes adaptation field (if present) payload (if present)
transport packet header 0 1 0 0 0 1 1 1 1st byte
sync byte 4th byte MSB transport_error_indicator LSB
MGR605
Fig.7 Transport packet header structure.
2000 May 19
15
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
Pins PDO0 to PDO7 and PDOCLK are normally part of the transport stream output interface. The signals to these pins are normally routed via an internal multiplexer. However, in the ITU656 bypass mode, these pins connect directly to the lower 8 bits of ADIN9 to ADIN0 and ADCLK. In this mode, PDOSYNC and PDOVAL are kept LOW and the polarity of PDOERR depends on the setting of I2C-bus bit FPBP. If required, these transport stream interface outputs can be forced to 3-state mode by making I2C-bus bit TSO = 0 (see Table 14). ITU656 bypass mode is enabled by setting the I2C-bus TSMODE bits to 10. SEGMENT ERROR COUNTER The TDA8961 transport stream output interface is able to calculate the Segment Error, or packet error, Rate (SER) over a certain time period. The time period can be set to either 1, 4, 8 or 16 seconds by the I2C-bus bits SERTM (see Table 14). The IC counts any packet errors occurring in the set time period. At the end of the time period, the 16-bit value representing the counted number of packet errors can be read via I2C-bus bit SER (see Table 19). After a reset, the register value is set to 12935 (3287H) which is equivalent to an infinite SER. The TDA8961 is able to automatically reset itself when the SER exceeds a preset threshold value. The SER threshold is a 14-bit value programmable in the range 3 to 13000 represented by I2C-bus bits SER_THRES (see Table 14). It should be noted that the time period set by the SERTM bits should be long enough to allow this threshold to be reached. This reset function is enabled by setting I2C-bus bit SER_RST (see Table 14). The reset function is disabled by default. Boundary scan interface The TDA8961 TAP conforms to the IEEE 1149.1 (JTAG) standard. It is used for board-level testing and for internally testing integrated circuits. The JTAG standard defines the on-chip test logic which comprises an instruction register, a group of test data registers including a bypass register and a boundary scan register, four dedicated pins comprising the TAP, and a TAP controller.
SCL SDA
TDA8961
EXTERNAL INTERFACE The TAP external interface has five pins whose functions are described in Table 4. Table 4 TAP external interface DESCRIPTION Test mode select input Test clock signal input Test data input Test data output Test asynchronous reset input
SIGNAL TMS TCK TDI TDO TRST I2C-bus interface
The I2C-bus interface writes control information to, and reads low-speed diagnostic information from the TDA8961. The key features of the I2C-bus interface are: * I2C-bus data rate of up to 400 kbits/s * Support for only 7-bit addressing and the ability to externally modify the slave address. A typical system using the I2C-bus interface is shown in Fig.8. The TDA8961 is acting as a slave and is connected to a master via the I2C-bus lines SCL and SDA. It should be noted that the SCL and SDA lines are connected to separate pull-up resistors.
handbook, halfpage
VDD
I2C-BUS MASTER
TDA8961
Rpu
Rpu
MGU089
Fig.8 Typical I2C system implementation.
2000 May 19
16
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
EXTERNAL INTERFACE The external interface has three pins whose functions are described in Table 5. Table 5 I2C-bus external interface DESCRIPTION I2C-bus I2C-bus serial data input/output clock input I2C-bus
TDA8961
A write operation is shown in Fig.9. The master transmitter sends a START condition followed by the 7-bit slave address which is followed by bit R/W set to 0. The slave receiver (TDA8961) responds by sending an acknowledge. The master then sends write data starting at address zero. If the master sends more than one byte of write data, the TDA8961 automatically increments to the next address. The TDA8961 sends an acknowledge after it receives each byte. If the TDA8961 does not acknowledge the data transfer and/or the master sends a STOP condition, the data transfer stops. It should be noted that the TDA8961 does not support I2C-bus sub-addressing. Therefore, each I2C-bus transfer starting with the transmission of the slave address and bit R/W, starts at address zero. A read operation is shown in Fig.10. The master transmitter sends a START condition followed by the 7-bit slave address which is followed by bit R/W set to 1. The slave receiver (TDA8961) responds by sending an acknowledge and the value at address zero. The master responds by sending an acknowledge. If the master follows the acknowledge with a STOP condition, the data transfer stops, otherwise the slave is allowed to transfer more bytes. The slave TDA8961 automatically increments to the next address of read data to be sent to the master.
SIGNAL SDA SCL A0 A1
I2C-bus slave address input bit 0 I2C-bus slave address input bit 1
The TDA8961 I/O and I2C-bus signals range between ground and 3.3 V. Systems that have devices which operate at different supply voltages may require special circuitry to allow these devices to communicate and to be controlled. Circuit requirements are described in "Application Report AN97055" (issued Aug. 04, 1997) available from Philips Semiconductors. ADDRESSING THE DEVICE The TDA8961 must be addressed by its 7-bit (A6-A0) slave address sent via the system I2C-bus in accordance with the correct protocols, and with bit R/W set to either 1 (write data) or 0 (read data). The slave address of the TDA8961 is given in Table 6. Bits A6 to A2 are preset, but bits A1 and A0 can be set via their corresponding external pins. Table 6 A6 0 TDA8961 slave address A5 0 A4 0 A3 1 A2 1 A1 A1 A0 A0 R/W 0 = write 1 = read
2000 May 19
17
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
TDA8961
handbook, full pagewidth
(1)(2)
(1)
(1)(3)
(4)(5)
(1)
(4)(5)
(1) (4)(5)(6)
(1)(7)
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A/A
P
(8)
MGR607
(1) (2) (3) (4)
From master to slave S = START condition Logic 0 (write) From slave to master
(5) (6) (7) (8)
A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) P = STOP condition Data transferred (n bytes + acknowledge).
Fig.9 Master transmitter addressing a slave receiver with a 7-bit address (write mode).
handbook, full pagewidth
(1)(2)
(1)
(1)(3)
(4)(5)
(4)
(1)(5)
(4)
(1)(6)
(1)(7)
S
SLAVE ADDRESS
R/W
A
DATA
A
DATA
A
P
(8)
MGR608
(1) (2) (3) (4) (5)
From master to slave. S = START condition. Logic 1 (read). From slave to master. A = acknowledge (SDA LOW).
(6) A = not acknowledge (SDA HIGH). (7) P = STOP condition. (8) Data transferred (n bytes + acknowledge).
Fig.10 Master transmitter addressing a slave receiver with a 7-bit address (read mode).
2000 May 19
18
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ATSC Digital Terrestrial TV demodulator/decoder
Table 7
I2C-bus write register overview ADDRESS (HEX) 00 01 02 03 04 D7 D6 D5 EQ_RST_ DISABLE D4 EQ_FREEZE D3 EQ_RESET AGC_RESET D2 BE_RESET CR_RESET D1 GNRL_RESET TR_RESET D0 INITIAL_ RESET SR_RESET
FUNCTION General settings
SRC AGC/ Carrier recovery
05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 MSE_THR_1[15 to 8] MSE_THR_1[7 to 0] MSE_THR_2[15 to 8] MSE_THR_2[7 to 0] AGC_ SAMPLES AGC_DIR AGC_TR_LOW CR_INV
AD_FMT
Objective specification
TDA8961
17 18 19 1A
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ATSC Digital Terrestrial TV demodulator/decoder
D7
D6
D5
D4
D3
D2
D1
D0
2E 2F 30 31 32 32 33 34 FTEI FPBP FDVP SER_RST TSO TSMODE SER_THRES[13 to 8] SER_THRES[7 to 0] PMSM SERTM Objective specification
TDA8961
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
Table 8 General settings (write) BIT VALUE 0 1 GNRL_RESET BE_RESET EQ_RESET EQ_FREEZE EQ_RST_DISABLE FE_RST_DISABLE SR_RESET AGC_RESET TR_RESET CR_RESET 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes 1. Operating modes and control parameters of all sections in the TDA8961 are not affected. normal operation (default) initial reset; note 1 normal operation (default) general reset; note 2 normal operation (default) backend reset normal operation (default) equalizer reset normal operation (default) equalizer adaptation freeze normal operation (default) equalizer reset disable normal operation (default) front-end reset disable normal operation (default) reset sync recovery section normal operation (default) reset input AGC normal operation (default) reset the timing recovery normal operation (default) carrier recovery reset enable DESCRIPTION
TDA8961
BIT NAME INITIAL_RESET
2. Operating modes and control parameters of all sections in the TDA8961 are reset to their initial values. Table 9 Sample rate converter settings (write) BIT VALUE 0 1 Table 10 AGC settings (write) BIT NAME AGC_SAMPLES AGC_DIR AGC_TR_LOW BIT VALUE 0 1 0 1 - average over 256 samples AGC operation compatible with TDA8980 (default) AGC operation compatible with TDA9819/9829 AGC threshold value DESCRIPTION average over 64 samples (default) two's complement binary (default) DESCRIPTION
BIT NAME AD_FMT
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
Table 11 Carrier recovery settings (write) BIT NAME CR_INV BIT VALUE 0 1 Table 12 Equalizer settings (write) BIT NAME MSE_THR_1 MSE_THR_2 BIT VALUE - - DESCRIPTION MSE loss-of-convergence threshold value 1 MSE loss-of-convergence threshold value 2 DESCRIPTION selects non-inverted spectrum; carrier at lower band-edge
TDA8961
selects inverted spectrum; carrier at higher band-edge (default)
Table 13 NTSC co-channel interference filter settings (write) BIT NAME FLT_BYPASS BIT VALUE 0 1 normal operation (default) bypass NTSC co-channel interference filter DESCRIPTION
Table 14 Transport stream interface settings (write) BIT NAME PMSM TSO FDVP BIT VALUE 0 1 0 1 0 1 FPBP FTEI 0 1 0 1 TSMODE 00 01 10 11 SERTM 00 01 10 11 SER_THRES SER_RST 0 1 parallel format (default) serial format transport stream outputs in 3-state mode transport stream outputs active (default) polarity of PDOVAL is LOW during the packet length of 188 data bytes polarity of PDOVAL is HIGH during the packet length of 188 data bytes (default) polarity of PDOERR goes LOW if block cannot be corrected polarity of PDOERR goes HIGH if block cannot be corrected (default) transport_error_indicator bit is not allowed to indicate any errors detected in the transport stream transport_error_indicator bit is allowed to indicate errors in the transport stream which could not be corrected by the Reed Solomon decoder (default) normal operation (default) reserved ITU656 bypass mode serialized transport input (pass-through mode) SER is calculated over a 1 second period (default) SER is calculated over a 4 second period SER is calculated over a 8 second period SER is calculated over a 16 second period SER threshold value (used if SER_RST is set to 1) normal operation (default) TDA8961 is reset when the SER exceeds 2.5 DESCRIPTION
2000 May 19
22
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
Table 15 I2C-bus read registers overview FUNCTION Basic operation Carrier recovery ADDRESS (HEX) 00 D7 D6 D5 D4 D3 D2 LOCK_I NDICAT OR CR_OFFSET[7 to 0]
TDA8961
D1 STATE
D0
01 02 03
Equalizer
04 05 06 07 08 09 0A
MSE[15 to 8] MSE[7 to 0]
Transport stream interface IC version(1) Note
0B 0C 0D TYPE[3 to 0]
SER[15 to 8] SER[7 to 0] VERSION[3 to 0]
1. This register allows the type and version of the TDA8961 to be read by the controlling host. The TYPE[3 to 0] field contains 1H corresponding to the TDA8961. The VERSION[3 to 0] field contains EH corresponding to the TDA8961 version N1E. Philips Semiconductors reserves the right to change the values in this register for future versions of the TDA8961. Table 16 General (read) BIT NAME STATE BIT VALUE 01 10 11 LOCK_INDICATOR 01 10 11 Table 17 Carrier recovery (read) BIT NAME CR_OFFSET Table 18 Equalizer (read) BIT NAME MSE 2000 May 19 BIT VALUE - DESCRIPTION Equalizer mean square error value 23 BIT VALUE - DESCRIPTION Carrier recovery offset value state 1 (channel acquisition) state 2 (equalizer training) state 3 (normal operation) channel acquisition: no synchronization; equalization locked equalizer training: synchronization locked; no equalization normal operation: synchronization locked; equalization locked DESCRIPTION
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
Table 19 Transport stream interface (read) BIT NAME SER BIT VALUE - segment error rate value DESCRIPTION
TDA8961
Table 20 TDA8961 version (read) BIT NAME TYPE VERSION BIT VALUE 0001 1110 1H = TDA8961 EH = TDA8961 version N1E DESCRIPTION
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134) SYMBOL VDD VI II IO Tj Tstg Tamb Ptot Ves PARAMETER supply voltage input voltage on any pin with respect to ground (VSS) DC current into any input DC current out of any output junction temperature storage temperature ambient temperature total power dissipation electrostatic handling note 1 note 2 Notes 1. Human body model: 2000 V (typical); C = 100 pF; R = 1.5 k; 3 zaps positive and 3 zaps negative. 2. Machine model: 200 V (typical); C = 200 pF; L = 0.5 H; R = 10 ; 3 zaps positive and 3 zaps negative. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 43 UNIT K/W CONDITIONS MIN. 3.0 -0.5 - - 0 - -20 - 2000 200 MAX. 3.6 VDD + 0.5 tbf tbf 125 - +70 - 4000 400 V V mA mA C C C W V V UNIT
QUALITY SPECIFICATION In accordance with quality specification: "SNW-FQ-611W".
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
DC CHARACTERISTICS VDD = 3.3 V; VSS = 0 V; Tamb = 25 C; unless otherwise specified; note 1. SYMBOL Supply VDD IDD Inputs VIL VIH ILI Ci Outputs VOL VOH IOL IO(Z) CO(Z) LOW-level output voltage HIGH-level input voltage LOW-level output current - 0.85VDD - - - - - - - - LOW-level input voltage HIGH-level input voltage input leakage current input capacitance - 2.0 - - - - - - supply voltage supply current 2.7 - 3.3 390 3.6 - PARAMETER CONDITIONS MIN. TYP.
TDA8961
MAX.
UNIT
V mA
0.2VDD - 1 25
V V A pF
0.4VDD - 4
V V mA A pF
3-state outputs (pins AGCOUT, PDO7 to 0, PDOCLK, PDOSYNC, PDOVAL and PDOERR) high-impedance output current high-impedance output capacitance 1 25
I2C-bus (pins SDA and SCL) VIL VIH VOL VOH IOL IL Ci Notes 1. All supply connections must be made to the same external power supply unit. 2. Open drain output, determined by VDD via an external pull-up resistor. LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage LOW-level output current leakage current input capacitance note 2 VOL = 0.4 V VI = VSS or VDD VI = VSS -0.5 0.7VDD 0 - 3 - - - - - - - - - +0.3VDD VDD + 0.5 0.4 VDD - 10 8 V V V V mA A pF
2000 May 19
25
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
AC CHARACTERISTICS VDD = 3.3 V; VSS = 0 V; Tamb = 25 C; unless otherwise specified. SYMBOL System clock (pin XTALI) fclk(sys) clk(sys) tsu(A/D) th(A/D) Tcy(ADCLK) tPDOCLKL(par) tPDOCLKH(par) system clock frequency system clock duty factor note 1 note 1 - - 5 5 27.8 12 50 - - - - - - - - - - - - PARAMETER CONDITIONS MIN. TYP.
TDA8961
MAX.
UNIT
MHz %
A/D interface (pins ADIN[9 to 0] and ADCLK); see Fig.11 A/D interface set-up time A/D interface hold time ADCLK cycle time ns ns ns
Transport stream interface (pins PDOCLK, PDO[7 to 0], PDOSYNC, PDOERR and PDOVAL) transport stream interface notes 2 and 3 PDOCLK LOW time; parallel format transport stream interface PDOCLK HIGH time; parallel format notes 2 and 3 166.7 166.7 ns ns
Tcy(PDOCLK)(par) transport stream interface notes 2 and 3 PDOCLK cycle time; parallel format tPDOVALH(par) tPDOVALL(par) td(o)(par) transport stream interface PDOVAL notes 3 and 4 HIGH time; parallel format transport stream interface PDOVAL note 3 LOW time; parallel format delay between transport stream interface outputs PDO to PDOVAL, PDOERR and PDOSYNC; parallel format transport stream interface PDOCLK LOW time; serial format transport stream interface PDOCLK HIGH time; serial format note 3
333.3 62666.7 - 0
- - - -
- - - -
ns ns ns ns
tPDOCLKL(ser) tPDOCLKH(ser)
notes 5 and 6 notes 5 and 6 notes 5 and 6 note 5
18.5 18.5 37.0 296.3
- - - -
- - - -
ns ns ns ns
Tcy(PDOCLK)(ser) transport stream interface PDOCLK cycle time; serial format tPDOSYNCH(ser) transport stream interface PDOSYNC HIGH time; serial format
tPDOVALH(ser) tPDOVALL(ser) td(o)(ser)
transport stream interface PDOVAL notes 5 and 7 HIGH; serial format transport stream interface PDOVAL note 5 LOW; serial format delay between transport stream interface outputs PDO to PDOVAL, PDOERR and PDOSYNC; serial format note 5
55703.7 - 0
- - -
- - -
ns ns ns
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8961
MAX.
UNIT
I2C-bus (pins SDA and SCL); see Fig.15 fSCL tBUF tHD;STA SCL clock frequency bus free time between a STOP and START condition hold time for a repeated START condition; after this period the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition set-up time for STOP condition data hold time data set-up time pulse width of spikes which must be suppressed by the input filter rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line note 8 0 1.3 0.6 - - - 400 - - kHz ms ms
tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tSP tr tf Cb td(TCK-TDO) tsu(i)(TCK) th(i)(TCK) tsu(PO)L Notes
1.3 0.6 0.6 0.6 0 100 tbf 20 + 0.1Cb 20 + 0.1Cb - 2 10 2
- - - - - - - - - - - - - -
- - - - 0.9 - tbf 300 300 400
ms ms ms ms ms ns ns ns ns pF
JTAG interface (pins TDO, TDI, TCK, TMS and TRST); see Fig.14 pin TCK to TDO valid delay input set-up time to TCK input hold time from TCK 10 - - - ns ns ns
Reset (pin RST_AN) power-on set-up time LOW 23 ns
1. The system clock signal is supplied by either an external 12 MHz crystal or another device such as the TDA8980 generating a stable 12 MHz clock signal. 2. When used for parallel format, the frequency of PDOCLK is 3 MHz. 3. See the timing measurement conditions in Fig.12. 4. This is calculated by multiplying 188 bytes (the length of a packet) by the PDOCLK clock cycle period. 5. See the timing measurement conditions in Fig.13. 6. When used for serial format, the frequency of PDOCLK is 27 MHz. 7. This is calculated by multiplying 188 bytes (the length of a packet) by the PDOCLK clock cycle period, multiplied by 8. 8. Cb = total capacitance of one bus line in pF.
2000 May 19
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
TDA8961
handbook, full pagewidth
Tcy(ADCLK)
ADCLK
t su(A/D)
t h(A/D)
ADIN9 to ADIN0
valid
MGU092
Fig.11 A/D interface timing.
handbook, full pagewidth
Tcy(PDOCLK)(par)
PDOCLK t PDOCLKL(par) t PDOCLKH(par) PDOSYNC
| t d(o)(par)|
PDOVAL t PDOVALH(par) PDOERR t PDOVALL(par)
PDO7 to PDO0
47H
MGU093
Fig.12 Transport stream interface timing (parallel output format).
2000 May 19
28
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
TDA8961
Tcy(PDOCLK)(ser) handbook, full pagewidth
PDOCLK t PDOCLKL(ser) t PDOCLKH(ser) PDOSYNC t PDOSYNCH(ser)
| t d(o)(ser)|
PDOVAL
t PDOVALH(ser) PDOERR
t PDOVALL(ser)
PDO0
0
1
0
0
1
1
1
1
MGU094
Fig.13 Transport stream interface timing (serial output format).
handbook, full pagewidth
TCK
t d(TCK-TDO)
t su(i)(TCK)
t h(i)(TCK)
TDO
valid
MGU095
Fig.14 JTAG I/O timing.
2000 May 19
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SDA t BUF t LOW tr tf t HD;STA t SP P = STOP condition. S = START condition. Sr = repeated START condition.
Philips Semiconductors
ATSC Digital Terrestrial TV demodulator/decoder
Fig.15 I2C-bus timing diagram.
handbook, full pagewidth
30
SCL t HD;STA P S t HD;DAT t HIGH t SU;DAT t SU;STA t SU;STO Sr
MBC611
P
Objective specification
TDA8961
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
PACKAGE OUTLINE QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
TDA8961
SOT318-2
c
y X
64 65
41 40 ZE
A
e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vMA Lp L detail X A A2 A1 (A 3)
80
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 REFERENCES IEC JEDEC MO-112 EIAJ EUROPEAN PROJECTION A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o
o
ISSUE DATE 97-08-01 99-12-27
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
TDA8961
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2000 May 19
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
Suitability of surface mount IC packages for wave and reflow soldering methods
TDA8961
SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable
2000 May 19
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Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
DATA SHEET STATUS DATA SHEET STATUS Objective specification PRODUCT STATUS Development DEFINITIONS (1)
TDA8961
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Preliminary specification
Qualification
Product specification
Production
Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. PURCHASE OF PHILIPS I2C COMPONENTS DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2000 May 19
34
Philips Semiconductors
Objective specification
ATSC Digital Terrestrial TV demodulator/decoder
NOTES
TDA8961
2000 May 19
35

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